CPLD is read and written to VHDL program by STM32

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3 -- This program is used to test the read and write operation of STM32 to CPLD

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5 -- Test functions are as follows:

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7 -- Write 0x01 to 0x05 address, the LED stops flashing, and other data will continue flashing

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9 -- 0x03,0x04 registers are fixed values, which can be read through STM32 and then output through serial port to see if they are consistent

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13 -- File name: AD.vhd

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15 library ieee;

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17 use ieee.std_ logic_ 1164.all;

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19 use ieee.std_ logic_ unsigned.all;

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23 entity AD is

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25 port(

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27 -- System signal line

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29 CLK: in std_ logic;

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31 LED: out std_ logic;

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33 -- Signal line connected to ARM

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35 Adr_ L: in std_ logic_ vector(7 downto 0); -- A7... A0, only the low-octet address line is used

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37 D: inout std_ logic_ vector(7 downto 0); -- Only the low-octet data line is used

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39 FSMC_ NE4: in std_ logic;

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41 FSMC_ NOE: in std_ logic;

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43 FSMC_ NWE: in std_ logic

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45 );

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47 end AD;

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51 architecture art of AD is

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53 -- Set register for storing data

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55 signal AD0_ H_ data,AD0_ L_ data,AD1_ H_ data,AD1_ L_ data,LED_ ctrl: std_ logic_ vector(7 downto 0);

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57 -- data buffer register

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59 signal data_ buf: std_ logic_ vector(7 downto 0);

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61 -- Data output control

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63 signal data_ outctl: std_ logic;

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65 signal datacnt:integer range 0 to 4000000;-- Frequency division count

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67 -- LED flashing enable

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69 signal LED_ flag: std_ logic;

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75 -- Unified address, address line data line is 8 bits, and each address data width is 8 bits

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77 --"00000001" AD0_ H_ data0x01

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79 --"00000010" AD0_ L_ data0x02

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81 --"00000011" AD1_ H_ data0x03

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83 --"00000100" AD1_ L_ data0x04

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85 --"00000101" LED_ ctrl0x05

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89 begin

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93 AD1_ H_ data <="10100001";

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95 AD1_ L_ data <="00010001";

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97 -- LED flashing, used as CPLD operation indicator

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101 process(LED_ctrl) is

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103 begin

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105 if(LED_ctrl="00000001") then

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107 LED_ flag <= '0';

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109 else

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111 LED_ flag <= '1';

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113 end if;

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115 end process;

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119 process(CLK)is

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121 begin

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127 if(CLK'event and CLK='1') then

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129 if(LED_flag='1') then

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131 datacnt<=datacnt+1;

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133 if (datacnt>2000000) then

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135 LED <= '1';

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137 end if;

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139 if (datacnt>=4000000) then

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141 LED <='0';

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143 datacnt <=0;

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145 end if;

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147 end if;

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149 end if;

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151 end process;

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155 -- Used to determine when to output data to the bus when reading CPLD data

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157 data_ outctl <= (not FSMC_NE4) and (not FSMC_NOE) and (FSMC_NWE);

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159 D <= data_ buf when (data_outctl='1') else "ZZZZZZZZ";-- Output data to the data line, otherwise it will remain in the high resistance state

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163 -- Write operation, mode 1, sequence diagram in data manual P331

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165 process(FSMC_NE4,FSMC_NWE,Adr_L,FSMC_NOE) is --,FSMC_ NBL,D,RESET

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167 begin

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169 if(FSMC_NWE'event and FSMC_NWE='1') then

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171 if((FSMC_NOE and (not FSMC_NE4))='1') then

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173 case (Adr_L) is

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175 when "00000001" =>

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177 AD0_ H_ data<= D; -- 0x01

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179 when "00000010" =>

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181 AD0_ L_ data<= D; -- 0x02

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183 when "00000101" =>

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185 LED_ ctrl<= D;-- 0x05

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187 when others =>

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189 AD0_ H_ data<= AD0_ H_ data;

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191 AD0_ L_ data<= AD0_ L_ data;

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193 end case;

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195 end if;

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197 end if;

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199 end process;

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203 -- Read operation, mode 1, P331

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205 process(FSMC_NE4,FSMC_NWE,Adr_L,FSMC_NOE) is

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207 begin

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209 if (FSMC_NOE='0 'and FSMC_NOE'event) then -- update data directly at the falling edge of NOE

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211 case (Adr_L) is

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213 when "00000001" =>

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215 data_ buf <= AD0_ H_ data; -- 0x01

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217 when "00000010" =>

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219 data_ buf <= AD0_ L_ data; -- 0x02

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221 when "00000011" =>

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223 data_ buf <= AD1_ H_ data; -- 0x03

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225 when "00000100" =>

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227 data_ buf <= AD1_ L_ data; -- 0x04

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229 when others => data_ buf <= "ZZZZZZZZ";

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231 end case;

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233 end if;

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235 end process;

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237 end;

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