Basic knowledge of integrated circuit packaging SOP packaging

What is SOP encapsulation?

Full English name of SOP: Small Outline Package, a surface-mount package in which the pins are led out from the two longer sides of the chip and the ends of the pins extend outward in the shape of gull wings

Naming rules of SOP

The package name of SOP is the same as that of DIP. The number after it indicates the number of pins in the package, such as SOP8, 8 indicates the number of pins (4 pins on both sides).

"Alternative" encapsulation of SOP

1. SOJ package

The full English name of SOJ: Small Outline J-Lead (small size J-shaped pin package). The pin is led out from both sides of the package and downward in a J-shape. Mainly used in memory, as shown in the following figure

2. SOIC package

The full English name of SOIC is Small Outline Integrated Circuit, which literally means SOIC=SOP. However, the editor found that the size of SOIC can be divided into wide and narrow according to the data of major manufacturers. Take TI's SN74HC595 as an example, as shown in the following figure:

The PDF data shows that the package size of SOIC16 is wide and narrow. After burning the universe of science and engineering, Xiaobian finally found that the standards followed by SOIC (JEDEC standard and EIAJ standard) were different, resulting in the same package but different sizes.

JEDEC and EIAJ standards

The full name of JEDEC is Joint Electronic Devices Engineering Council, which was established in 1958. The full name of EIAJ is Electronic Industries Association Japan, which was founded in 1948. These two companies set standards for the electronics industry, but the EIAJ standard's SOIC body width is 5.3mm, while the JEDEC standard's SOIC body width is 3.8mm or 7.5mm, which also leads to the size difference of SOIC. This difference is mainly reflected in the width WB and WL